Design and simulation of nanoscale tunneling field effect transistors for CMOS applications

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dc.contributor.advisorJagadesh Kumar, M.
dc.contributor.authorSneh Saurabh
dc.date.accessioned2012-07-24
dc.date.accessioned2024-10-29T11:16:12Z
dc.date.issued2011
dc.identifier.urihttp://10.17.50.146:4000/handle/123456789/3212
dc.relation.ispartofseriesTH4177
dc.subjectIntegrated circuit
dc.titleDesign and simulation of nanoscale tunneling field effect transistors for CMOS applications
dc.typeThesis

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