Optimizing neural networks performance on parallel architectures

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dc.contributor.authorTewari, Saurabh
dc.date.accessioned2024-12-10T08:24:12Z
dc.date.issued2024-01-01
dc.identifier.urihttp://ir.iitd.ac.in/handle/123456789/5413
dc.language.isoen
dc.publisherIIT Delhi
dc.subjectEnergy efficient N N inferencing | Architectural parameters | Off-chip memory accesses | Optimization problem | Future research directions
dc.titleOptimizing neural networks performance on parallel architectures
dc.typeThesis

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